FIG. 1 is a schematic diagram illustrating a configuration of a data processing apparatus 100 according to a related art example. The data processing apparatus 100 of the related art example includes a CPU (Central Processing Unit) 1, a cache memory 2, a control part 3, a main memory 4, a HDD (hard disk drive) 5, and a power source part 6. The cache memory 2, the control part 3, the main memory 4, and the HDD 5 are connected by a bus.
The CPU 1 reads, for example, a program or data stored in the HDD 5, performs a calculating process according to the program, and outputs a result of the calculation. The CPU 1 includes a register 1A which temporarily stores data such as data of addresses used when reading/writing from/to the calculation result or main memory 4.
Typically, a volatile register is used as the register 1A.
The cache memory 2, which is a high, speed small capacity memory that temporarily stores data, is connected to the CPU 1. Typically, a volatile memory is used as the cache memory 2.
The control part 3, which is controlled by the CPU 1, controls the sending/receiving of data between the cache memory 2 and the main memory 4.
The main, memory 4 reads data to be used by the CPU 1 from the HDD 5 and temporarily stores the read data. Typically, a volatile memory such, as DRAM (Dynamic RAM: a read/write memory that periodically requires a memory maintaining action such as refresh) is used as the main memory 4.
The HDD 5 is a large capacity storage apparatus for storing data such as programs required by the CPU 1 for performing a calculating process and data of the calculation results.
The power supply part 6 converts the voltage value of the voltage supplied from an external power supply and supplies electric power to the CPU 1, the register 1A, the cache memory 2, the control part 3, the main memory 4, and the HDD 5. The power supply part 6 is a large capacity condenser (capacitor) serving to maintain a power supply for reserving electric power required during a period of performing a data saving process (described below) in a case where an abnormality occurs in the power supply part 6. It is to be noted that the voltage value of the power supply part 6 is constantly monitored by the CPU 1.
Accordingly, with the data processing apparatus 100, the main memory 4 reads necessary programs and data stored in the HDD 5 and the CPU 1 performs various calculating processes using the programs and data stored in the main memory 4.
FIG. 2 is a flowchart, for describing processes performed by the CPU 1 where an abnormality occurs in a power supply system of the power supply part 6 of the data processing apparatus 100 according to the related art example.
The CPU 1 determines whether there is a decrease in the value of the voltage supplied from the power supply part 6 due to an abnormality (e.g., malfunction, power outage) based on the monitoring results input from the power supply part 6 (Step S1). Step S1 is repeated until a decrease in the value of the voltage supplied from, the power supply part 6 occurs.
In a case where the CPU 1 determines that there is a decrease in the value of the voltage supplied from the power supply part 6, the CPU 1 sets a power supply abnormality flag to “1” (Step S2).
The CPU 1 executes a data saving process in which data stored in the register 1A and data stored in the cache memory 2 are saved in the HDD 5. Then, the CPU 1 determines whether the data saving process is completed by determining whether the stored data of the register 1A and the stored data of the cache memory 2 have been stored in the HDD 5 (Step S3). Step S3 is repeated until the CPU 1 determines that the process of saving the stored data of the register 1A and the cache memory 2 into the HDD 5 is completed.
When the CPU 1 determines that the data have been stored in the HDD 5, the CPU 1 stores a process history of the CPU 1 in the HDD 1 (Step S4).
Then, the CPU 1 executes another data saving process in which data stored in the main memory 4 are saved in the HDD 5. Then, the CPU 1 determines whether the data saving process is completed (Step S5). Step S5 is repeated until the CPU 1 determines that the process of saving the stored data of the main memory 4 into the HDD 5 is completed.
Then, the CPU 1 stops all processes that are being executed (Step S6).
The processes are stopped so that the power supply part 6 can be, for example, replaced or repaired.
After the repairing or replacing of the power supply part 6 is completed, the data processing apparatus 100 is restarted. When the data processing apparatus 100 is restarted, the CPU 1 determines whether the power supply abnormality flag is “1” (Step S7). Step S7 is for determining whether a decrease of the value of the voltage of the power supply part 6 has occurred previous to the restarting of the data processing apparatus 100.
The CPU 1 deploys the stored data saved in the HDD 5 to the register 1A, the cache memory 2, and the main memory 4. Then, the CPU 1 determines whether the data deploying process is completed (Step S8). Step S8 is repeated until the CPU 1 confirms that the data deploying process is completed.
The CPU 1 resumes to a process that was being executed until the occurrence of the abnormality of the power saving part 6 (resuming of continuing program) (Step S9).
Accordingly, the data saving process and the restarting process where abnormality occurs in the power supply part 6 are completed. The power required during a period of the data saving process after the abnormality of the power supply part 6 is supplied from a large capacity condenser (capacitor) provided inside the power supply part 6 for maintaining power.
A data processing apparatus 300 according to another related art example is illustrated in FIG. 3. The data processing apparatus 300 is provided with a backup power supply (e.g., backup battery) 7 for supplying backup power to the main memory 4, so that data stored in the main memory (DRAM) 4 can be protected where an abnormality occurs in the power supply part 6.
Since approximately several seconds to several tens of seconds is required for performing the above-described data saving process, a large capacity condenser is necessary for maintaining power. Such a necessity results in an increase in the size and cost of the data processing apparatus 100, 300 of the related art examples. Particularly, since the main memory 4 has larger memory capacity than the register 1A or the cache memory 2, a long time is required in performing the data saving process for the main memory 4.
Further, in a restarting process after the recovery of the power supply part 6, the data processing apparatus 100, 300 of the related art examples cannot be immediately used due to the long time required in deploying the saved data. Particularly, in a case where immediate recovery of the data processing apparatus 100, 300 of the related art examples is required (e.g., a case where the data processing apparatus 100, 300 is for an institution used by many users), prompt recovery of the data processing apparatus 100, 300 is required for meeting the demands of the users.